1. Field of the Invention
The present invention relates to a semiconductor device, a semiconductor device testing method, and a data processing system, and more particularly relates to a semiconductor device constituted by a plurality of core chips and an interface chip that controls the core chips, a semiconductor device testing method, and a data processing system.
2. Description of the Related Art
A memory capacity that is required in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) are increasing every year. To satisfy this requirement, in recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested. However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device (memory controller, for example) is included in each memory chip. For this reason, the occupied area assignable for a memory core in each of the memory chips is limited to an area obtained by subtracting an occupied area for the front end unit from the whole chip area. Therefore, it is difficult to greatly increase a memory capacity for each chip.
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there have been a further problem that it is difficult to speed up the front end unit.
As a method to resolve the above problem, a method that integrates the front end unit and the back end unit separately in discrete chips and laminates these chips, thereby constituting one semiconductor memory device, is suggested. According to this method, with respect to core chips in which the back end unit is integrated, it becomes possible to increase a memory capacity for each chip because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit and is common to the plural core chips, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor memory device that has a large memory capacity and a high operation speed as a whole.
In a semiconductor device using an interface chip, adjacent chips are electrically connected to each other by a large number of through silicon vias passing through substrates of core chips. Most of the through silicon vias are short-circuited to through silicon vias in other layers provided at same positions as seen in a planar view from a laminated direction. A current path for connecting the interface chip to each core chip is formed by a group of electrically short-circuited through silicon vias.
Japanese Patent Application Laid-open No. 2009-139273 discloses a testing technique for confirming a connection state of an internal terminal connecting a through silicon via to an internal circuit, although this is an example of a multi-chip package. According to the laminated configuration of this technique, internal terminals at the same position of a plurality of isomorphic memory core chips 2 are connected to each other via through silicon vias 4 with internal terminal junctions 3. These internal terminals are connected to an external terminal 5 by a wiring on an interposer chip 1 (not shown). The interposer chip 1 includes a unit that connects a wiring pattern to the external terminal 5 (for example, a through silicon via and a bonding pad (not shown)). This unit has a function to convert a position of the internal terminal with a position of the external terminal 5. That is, the external terminal 5 of the semiconductor device is electrically directly connected to any of the internal terminals that serve as a terminal to be measured in the semiconductor device. According to this testing technique, in the wiring configuration, a conduction check diode is provided in the midway of an internal wiring connecting the internal terminal to the internal circuit for each internal terminal, and its cathode side is connected to the internal wiring. A conduction test dedicated terminal is provided at an external terminal of a corresponding multi-chip package (a semiconductor device) for each memory chip and an anode of each conduction check diode within a same memory chip is commonly connected to the conduction test dedicated terminal. When the connection state of a certain internal terminal is tested, a voltage of −1 V is applied to a current path including the corresponding through silicon via through the external terminal and a voltage of 0 V is applied to the corresponding conduction test dedicated terminal. As a result, a forward current of the conduction check diode flows through the current path when the internal terminal is properly connected and the current does not flow when the internal terminal is disconnected. Therefore, by measuring the current appearing in the external terminal using a tester outside the semiconductor device, whether the internal terminal within the semiconductor device is properly connected can be determined.
In a semiconductor device using an interface chip, a parasitic resistance value of a current path including through silicon vias may become excessively large. When the parasitic resistance value is excessively large, characteristics of the semiconductor device are deteriorated. Accordingly, it is desirable to measure the parasitic resistance value of the current path with high precision.
Paragraph [0010] of Japanese Patent Application Laid-open No. 2009-139273 describes a resistance value. As is understood from this description, the technique of this conventional technique is merely a technique of determining “whether the internal terminal including the through silicon via is disconnected (=whether the resistance value is infinite)” by the test circuit. The technique of Japanese Patent Application Laid-open No. 2009-139273 cannot be applied to a semiconductor device using an interface chip that an external terminal of the semiconductor device is not electrically directly connected to a terminal to be measured within the semiconductor device. This is because in the semiconductor device using an interface chip, a current path including a through silicon via to be measured is an internal signal line that is not connected to outside of the semiconductor device and lines that are not connected to the external terminal are also included. When the interface chip has a signal processing function, a signal of an internal wiring to be measured is subject to signal processing by a logic circuit in the interface chip and an output signal of that logic circuit is outputted as an external terminal. Meanwhile, an externally inputted signal is subjected to the signal processing in the interface chip and outputted to the internal wiring to be measured. Accordingly, application of −1 V of voltage through the external terminal and measurement of the current appearing in the external terminal as disclosed in Japanese Patent Application Laid-open No. 2009-139273 cannot be performed.
In a semiconductor device using an interface chip that an external terminal of the semiconductor device is not electrically directly connected to a terminal to be measured in the semiconductor device, it has been desired to determine the magnitude of parasitic resistance value of an internal signal line including through silicon vias from outside of the semiconductor device.